Embodiments of the invention relate generally to chip packages and, more particularly, to chip packages having vias formed through dielectric and adhesive layers down to die pads of an electronic chip, with the vias having stress-resistant metal interconnects formed therein having an increased thickness.
Advancements in integrated circuit (IC) chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization and higher reliability. Most semiconductor devices, such as bare chips, have electrical contact pads or “die pads” located on a top-side or active surface of the device to provide input/output (I/O) connections. IC chips first packaging technologies such as the embedded chip build-up process (ECBU), generally apply a first dielectric layer (e.g., polyimide film) over a chip top surface, form vias in the dielectric layer such that they abut the die pads on the chip, and then form metal interconnections to the die pads along the vias and metal cover pads about the via openings on a top surface of the dielectric layer. For yield and reliability issues, the metalized cover pad generally extends beyond the opening of the via. This additional level of interconnection redistributes the peripheral bonding pads of each chip to an area array of metal pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these metal pads.
As functionality on ICs/chip packages continues to increase, the number of die pads on the chip is increased and the pad pitch (i.e., the center-to-center distance between adjacent die pads) is reduced, such as to 50 micrometers or less. This reduces the space available for via interconnect to the device, forcing smaller vias to be used (i.e., vias having a smaller diameter). Often, the thickness of dielectric layers applied to the chip cannot be reduced, either because of impedance requirements between high frequency layers or due to dimension rigidity needed for pattern overlay alignment. Thus, while the diameter of the vias is reduced, the height/thickness of the vias extending through the dielectric layer remains somewhat constant, thereby resulting in vias having an increased aspect ratio (i.e., height-to-diameter ratio). Smaller diameter vias, however, are harder to fill with metal during electroplating, and the total volume of metal present within such vias may be less for a given thickness compared to larger vias. That is, while the metal cover pads about the via openings on the top surface of the dielectric layer may be of a given thickness, the thickness of metal present within a smaller diameter via may be less than the given thickness based on the smaller diameter and an increased aspect ratio, thus reducing the volume of metal in the via below what is desired.
This reduced volume of metal present in a reduced diameter via can lead to durability issues with the metal interconnect. That is, during thermal cycling reliability testing, stress from coefficient of thermal expansion (CTE) mismatch between the metal in the vias and the surrounding dielectric material eventually causes metal fatigue and cracking, resulting in loss/failure of the metal interconnect. This happens more quickly if there is less total metal present to minimize fatigue.
Accordingly there is a need for a system and method of chip packaging that provides for reliable metal interconnect connection to die pads on a chip. There is a further need for such metal interconnects to resist fatigue caused by thermal stress, especially in high density interconnect (HDI) IC packages that include vias with a reduced diameter and increased aspect ratio.